Due to the continuing increase in integration density of semiconductor devices, it has been increasingly necessary to fabricate semiconductor devices having metal interconnection layers with a multi-layer structure and with smaller distances between the metal interconnection layers. In accordance with these trends, parasitic resistance (R) and capacitance (C) components, which exist between horizontally or vertically adjacent metal interconnection layers, have become primary factors that are considered in the design and manufacture of semiconductor devices due to the adverse effects that such components can have on operation of semiconductor devices.
Indeed, parasitic resistance and capacitance components in a metal interconnection framework may cause, e.g., signal delay, which can deteriorate the electrical performance of a semiconductor device. In addition, parasitic resistance and capacitance components can increase the total power consumption of a semiconductor chip and increase the amount of signal leakage from the semiconductor chip. Therefore, it is important to develop a multi-layer interconnection framework that can provide smaller parasitic resistance and capacitance in a highly integrated semiconductor device.
To form a multi-layer interconnection structure having smaller parasitic resistance and capacitance, an interconnection layer should be formed using a metal having a low specific resistance, such as copper (Cu), and/or using an insulation layer having a small dielectric constant. However, it has proven difficult to form a Cu interconnection layer using a typical photolithography-based patterning process. Therefore, dual damascene processes have generally been implemented for forming Cu interconnection layers.
FIGS. 1 through 3 are cross-sectional schematic views illustrating a conventional method for forming a metal interconnection layer of a semiconductor device. Referring to FIG. 1, a first stopper layer 104, a first interlayer dielectric layer 105, a second stopper layer 106, and a second interlayer dielectric layer 107 are sequentially formed on a semiconductor substrate 100 having a first conductive layer 102. A full via hole 112 is formed having a first width W1 by sequentially etching the second interlayer dielectric layer 107, the second stopper layer 106, and the first interlayer dielectric layer 105 using a photolithography process.
Thereafter, a photoresist layer is deposited on the entire surface of the substrate, filling the full via hole 112 with photoresist material. Then, a photoresist pattern 110 is formed by light-exposing and developing the photoresist layer, to thereby provide an opening having a second width W2 which exposes part of the second interlayer dielectric layer 107 and part of the full via hole 112. Here, the second width W2 is larger than the first width W1. As depicted in FIG. 1, a portion of the photoresist layer remains in the full via hole 112.
Referring now to FIG. 2, the second interlayer dielectric layer 107 is dry-etched using the photoresist pattern 110 as an etching mask until the top surface of the second stopper layer 106 is exposed. As a result of the dry etching, a trench interconnection area 114 of width W2 is formed in the second interlayer dielectric layer 107. In addition, the dry etch process results in further etching of the photoresist layer in the full via hole 112.
Referring now to FIG. 3, the photoresist layer remaining in the full via hole 112 and the photoresist pattern remaining on the second interlayer dielectric layer 107 are removed using a conventional ashing process. Thereafter, the portion of the first stopper layer 104 that is exposed at the bottom of the full via hole 112 is removed, and a second conductive layer (not shown) is formed in the full via hole 112 and the trench interconnection area 114, thereby forming a dual damascene structure.
There are various disadvantages associated with the conventional method depicted in FIGS. 1–3. For example, because of variations in the thickness of the photoresist layer from region to region of the substrate, which is due to filling the full via holes 112 and different density of the via holes 112 in between the regions, it is very difficult to control the critical dimensions (CD) and the profile of the first photoresist pattern 110 using a photolithography process. In addition, the photoresist material in the full via hole 112 may not be successfully developed, which can prevent the second interlayer dielectric layer 107 from being fully etched away, resulting in formation of the fence 116 along the via hole 112 in the trench interconnection area 114. The fence 116 can result in a poor electrical connection between the first conductive layer 102 and the second conductive layer that fills the via hole and trench interconnection area.
FIGS. 4, 5 and 6 are cross-sectional schematic views illustrating another conventional method for forming a metal interconnection layer of a semiconductor device. Referring initially to FIG. 4, a first stopper layer 104, a first interlayer dielectric layer 105, and a second interlayer dielectric layer 107 are sequentially formed on a semiconductor substrate 100 having a first conductive layer 102. Thereafter, a full via hole 112 is formed having a first width W1 by sequentially etching the second interlayer dielectric layer 107 and the first interlayer dielectric layer 105 using a photolithography process. Then, a sacrificial layer 116, which comprises an organic or inorganic material, is deposited to fill a least a portion of the full via hole 112 A photoresist layer is then deposited on the entire surface of the substrate, filling the remaining portion of the full via hole 112. Then, a photoresist pattern 110 is formed by light-exposing and developing the photoresist layer, to thereby provide an opening having a second width W2 which exposes part of the second interlayer dielectric layer 107 and part of the full via hole 112. Here, the second width W2 is larger than the first width W1. As depicted in FIG. 4, a portion of the photoresist layer remains in the full via hole 112.
Referring now to FIG. 5, the second interlayer dielectric layer 107 is partially etched using the photoresist pattern 110 as an etching mask. As a result of the etching, a trench interconnection area 114 having the second width W2 is formed in the second interlayer dielectric layer 107. In addition, the dry etch process results in further etching of the photoresist layer in the full via hole 112 according to its etching selectivity with respect to the second interlayer dielectric layer 107. After the dry etch process, the photoresist layer 110 and the sacrificial layer 116 still remain in the full via hole 112.
Referring now to FIG. 6, the photoresist pattern 110 is removed, and then the sacrificial layer 116 remaining in the full via hole 112 is removed. Thereafter, the portion of the first stopper layer 104 exposed at the bottom of the full via hole 112 is removed, and then a second conductive layer (not shown) is formed in the trench interconnection area 114, thereby forming a dual damascene structure.
There are various disadvantages associated with the conventional method illustrated by FIGS. 4–6. Although the method can, to some extent, resolve the problem of varying thickness of the photoresist layer from region to region due to variation in the density of via holes 112, such method may still result in generation of the fence 116 along the via hole 112 (see FIG. 6) when the sacrificial layer 116 is formed of a bottom anti-reflection coating (BARC) material or is formed of the same organic material used to form the photoresist layer 116. Furthermore, when the sacrificial layer 116 is formed of an inorganic material, such as hydrogen silsesquioxane (HSQ), there is a need to further perform a stripping process to remove the sacrificial layer 116, which is a very complicated and difficult process.